Falling. Table 1: Clock Modes sampling and shifting. 1. SPI Mode 0 - CPOL : 0, CPHA : 0. Figure 3.2: SPI Mode 0. Data is sampled on the rising edge and shifted out on the falling edge of the clock signal. Here, the clock polarity is low in the ideal state; when no data is being transferred, the clock line is low. 2.